Net is graphically connected to a bus but not a bus member

Q: Why does ERC flag only the zero-padded members of my bus?

Vector bus expansion does not pad numbers: BA[00..23] produces members BA0 through BA23. A wire labeled BA00 is therefore a different net name and not a member. Drop the padding from the wire labels, or define a group bus listing the padded names explicitly.

What this error means

The check fires on bus entries, the 45° stubs that step a wire onto a bus. For every net that reaches a bus through one, ERC takes the bus's member list — D[0..7] expands to D0 through D7, group buses like {SCL SDA} are expanded one level — and looks the net's name up in it. No match, one warning, with the marker on the bus entry.

The name is the entire test. A bus carries a signal only between points that drop it onto the same member name; the entry and the touching lines are graphics, the labels are the netlist. The warning means no member connection will come of this wire.

Two net types are exempt. If the offending wire is named by a global label or a power symbol, the warning is suppressed, because those name the net schematic-wide and the bus is not expected to carry it.

Common causes

1. The wire's label doesn't match any member

The common case: CLK wired into D[0..7], a typo like BA_0 for BA0, or the wrong prefix after copying a block. Zero padding is a subtle variant — BA[00..23] expands to BA0…BA23, so a wire labeled BA00 is not a member of its own bus.

2. The bus itself has no label, or its label isn't bus syntax

An unlabeled bus has no members, so every entry into it warns; the report gives the bus's name as <NO NET>. A label without [m..n] or {...} doesn't define members either — it makes the line a net item and trips bus_to_net_conflict instead.

3. A foreign net is routed into the bus on purpose

Drawing an unrelated signal into the bus bundle to keep the sheet tidy, or trying to join TX to RX "through" the bus. Buses never rename a net: a signal enters and leaves under one member name.

How to fix it

Rename the net to an actual bus member

Read the warning: it names both the net and the bus, e.g. Net /CLK … bus /D[0..7].
Spell out the expansion of the bus label. D[0..7] contains D0 through D7 — no zero padding, no D8.
Edit the wire's label (hover, E) to one of those exact names, then re-run ERC (Inspect → Electrical Rules Checker).

Use when: The wire belongs in the bus and the name is off by a typo, a prefix, or a padded zero. In the checked-in repro, renaming `CLK` to `D3` drops the warning on both KiCad 9 and 10.

Give the bus a label that contains the members you use

Put a label on the bus wire with vector syntax (ADDR[0..15]) or group syntax ({SCL SDA} or USB{DP DM}).
For a group used on many sheets, define it once under File → Schematic Setup → Bus Alias Definitions and label the bus with the alias name.
Re-run ERC and check the other entries too — an unlabeled bus warns on every one.

Use when: The report says `bus /<NO NET>`, or the member list the label defines is narrower than what you wired in.

Unfold members instead of wiring entries by hand

Hover the bus and press C (or right-click → Unfold from Bus).
Pick the member from the list; KiCad places the entry, the wire, and a correctly named label in one move.
Finish the wire at the destination pin.

Use when: You are breaking out several members and want the names guaranteed to match. Works the same in KiCad 9 and 10.

When it’s safe to exclude

Sometimes defensible, which is why it ships as a warning rather than an error. Connectivity comes from the labels, so a schematic where the names match up elsewhere can netlist correctly while a decorative bus line collects these warnings. If the bus is pure decoration, though, the better fix is extending its label to list what actually runs through it — then the warnings vanish and the bus means something.

Excluding a single marker (right-click → Exclude this violation) or downgrading the whole check in Schematic Setup → Electrical Rules → Violation Severity hides the typo case, and the typo case is nasty: the signal silently never joins its bus, and the first symptom is an unconnected net in the PCB editor. Exclude per-marker if you must; keep the check on.

Gotchas

No warning is not proof of membership. Nets named by a global label or a power symbol are skipped entirely, so a global-labeled wire can sit in a bus it has nothing to do with and ERC stays quiet.
A bus entry connects on the wire side only at a wire endpoint. Land it mid-wire — junction dot and all — and you get unconnected_wire_endpoint instead of a connection.

Minimal reproduction

Draw a bus (B), label it D[0..7], and drop a wire onto it through a bus entry (Place → Place Wire to Bus Entries, hotkey Z). Label the wire CLK, wire its other end to any pin, and run ERC (Inspect → Electrical Rules Checker):

[net_not_bus_member]: Net /CLK is graphically connected to bus /D[0..7] but is not a member of that bus
    ; warning

The checked-in file data/erc/samples/net_not_bus_member.kicad_sch reproduces this with two embedded one-pin symbols terminating the CLK wire. Because the file embeds its own symbols, the run also emits two lib_symbol_issues warnings about the missing repro library; those are artifacts of the self-contained sample. Renaming the CLK label to D3 drops the report to the two artifact warnings on both KiCad 9.0.8 and 10.0.6 — fix #1 in miniature.

FAQ

Why does ERC flag only the zero-padded members of my bus?

Vector bus expansion does not pad numbers: BA[00..23] produces members BA0 through BA23. A wire labeled BA00 is therefore a different net name and not a member. Drop the padding from the wire labels, or define a group bus listing the padded names explicitly.

The netlist and PCB look right, so is this warning wrong?

Often the design still works, because KiCad connects bus members by matching labels, not by the drawn entry — if the names agree somewhere else, the net forms anyway. The warning is pointing at a wire whose name the bus does not contain, which is either a dead decoration or a typo about to cost a board spin. Check the name before dismissing it.

Can I connect an input to an output with different net names via a bus?

No. A bus never renames a signal: a connection forms only where both ends drop onto the same member name. To route one chip's TX into another's RX, pick a single net name such as UART_TX, label both breakout wires with it, and make it a member of the bus.

Do I have to put a label on the bus itself?

Yes, if anything connects to it through bus entries. The label is what defines the member list; an unlabeled bus has no members, shows up as <NO NET> in this warning, and flags every wire that enters it. One vector or group label on any segment of the bus is enough.

Sources

Reviewed against KiCad 10.0.6 on October 19, 2026 and KiCad 9.0.8 on October 19, 2026. Every claim on this page was checked with kicad-cli sch erc.