What this error means
ERC runs this check on each connected set of bus wires. Within the set it picks the first global label that names a bus and the first hierarchical item on the same bus — a sheet pin or hierarchical label — and compares their member lists. Sharing a single member name is enough to pass. Sharing none fails, and the marker anchors to the global label and the sheet pin.
The two lists can only disagree when a bus crosses a hierarchy boundary
carrying its own global label on each side. A[0..3] on the parent sheet
expands to A0…A3; a global label C[0..3] on the child side of the same
bus expands to C0…C3; nothing overlaps, so KiCad has no way to decide
which name the members should get in the netlist. In the repro below the
members do still connect, but they come out named C0…C3 — the child's
label silently wins, and nothing on the parent sheet says C anywhere.
The sheet pin's own name never enters the comparison. A pin can rename a
bus across the boundary (A[0..3] outside, B[0..3] inside) and KiCad
maps the members through it without complaint; that is supported and is
not what this error is about.
Common causes
1. The same bus has a different global label on each side of a sheet boundary
Almost always a naming drift: the top sheet labels the bus
DATA[0..7], and inside the subsheet the same bus wire picked up its
own global label with another prefix — often left over from a subsheet
that was copied in from a different project. Both labels are global
naming authorities, so neither side gives way.
2. Two genuinely unrelated buses are joined through a sheet pin
Less common: a bus wire was dragged onto a sheet pin that belongs to a different bus. Here the error is correct in the strongest sense — look at what the pin carries before touching any labels.
How to fix it
Use one bus name on both sides of the boundary
- Open the marker; it points at a global label and a sheet pin. Note the two bus names involved.
- Double-click the global label on one side (usually the subsheet's) and rename it to the name the other side uses, e.g. both `A[0..3]`.
- Re-run ERC (Inspect → Electrical Rules Checker).
Use when: The two labels were always meant to be the same bus. Matching names exactly is the answer; technically one shared member silences the check, but a partial overlap is a renaming job half done.
Delete the redundant global label and let the sheet pin carry the bus
- Select the global label on the subsheet's bus wire and delete it.
- Leave the hierarchical label / sheet pin pair in place — it maps the members across the boundary on its own.
- Re-run ERC.
Use when: The bus already travels through a hierarchical label and sheet pin, so a second, global name on the same wire adds nothing. This also clears the `multiple_net_names` warning that usually accompanies this error.
When it’s safe to exclude
Don't. This check fires so rarely in KiCad 9 and 10 that when it does, it
has found a real naming conflict, and the consequence is concrete: the
netlist names of every member are decided by whichever label wins
internally, not by anything you can see on the sheet where you labeled the
bus. In the checked-in repro the members come out as C0…C3 although the
parent sheet only ever says A[0..3]. Renaming one label costs seconds;
if you truly must silence a single instance, right-click the marker →
Exclude, but a severity downgrade in Schematic Setup → Electrical Rules →
Violation Severity buys you nothing here.
Gotchas
- Renaming the sheet pin does not fix it. The pin's own name is never compared; the check weighs the parent-side global label against the name the child side resolved to. A pin named to match the parent label still errors if the child bus keeps its conflicting global label.
- Only global labels trigger it. The identical conflict built with a
local label on the parent bus produces no
bus_to_bus_conflict, just themultiple_net_nameswarning. Silence from this check is not evidence your bus naming is consistent. - One shared member is a pass:
A[0..3]againstA[2..5](sharingA2,A3) raises nothing, even though half of each bus maps to nowhere.
Minimal reproduction
Draw a bus wire on the root sheet, attach a global label A[0..3], and
wire the bus into a subsheet through a sheet pin B[0..3]. Inside the
subsheet, attach the matching hierarchical label B[0..3] to a bus wire —
so far ERC is clean. Now add a global label C[0..3] to the subsheet's
bus wire and re-run ERC (Inspect → Electrical Rules Checker):
[bus_to_bus_conflict]: Buses are graphically connected but share no bus members
; error
@(101.60 mm, 101.60 mm): Global Label 'A[0..3]'
@(120.65 mm, 101.60 mm): Hierarchical Sheet Pin 'B[0..3]'
The checked-in files data/erc/samples/bus_to_bus_conflict.kicad_sch
(root) and bus_to_bus_conflict_sub.kicad_sch (subsheet) reproduce
exactly this. The same run also emits a multiple_net_names warning on
the subsheet — C[0..3] and B[0..3] naming the same wire — which is
part of the same disease, not an artifact. Renaming the subsheet's global
label from C[0..3] to A[0..3] drops the error on both KiCad 9 and 10,
which is fix #1 in miniature.
Related errors
- Invalid connection between bus and net items
- Conflict between bus alias definitions across schematic sheets
- More than one name given to this bus or net
- Mismatch between hierarchical labels and sheet pins
FAQ
Can I connect a bus across sheets with a global label?
Yes — a global bus label like DATA[0..7] joins its bus on every
sheet where it appears. The conflict only starts when the same bus
wire is also named something else: a second global label with
different members on the far side of a sheet pin. Pick one global
name per bus, or drop the global label and route the bus through
hierarchical labels and sheet pins instead.
Why does ERC complain when I pass a bus from a child sheet to its parent?
Passing a bus through a hierarchical label and sheet pin is fine, and the pin may even use a different prefix than the parent bus. The error means something extra: each side of the boundary carries its own global bus label, and the two expand to member sets with no names in common, so KiCad cannot pick netlist names for the members.
Do the bus names on the parent sheet and the subsheet have to match?
Not when the renaming happens at the hierarchy junction itself. A bus
labeled A[0..3] wired to a sheet pin B[0..3] connects member to
member, and ERC accepts it. What must agree are global labels, which
claim their name everywhere: two global labels with disjoint members
on one connected bus produce this error.