What this error means
This is a KiCad 9 check; KiCad 10 removed it (see the version note below). ERC walks each net segment, skipping buses, and reports a global label in two situations:
- The label's anchor is not attached to any wire or pin at all. In KiCad 9
an unattached global label reports under this code, where local and
hierarchical labels report
label_dangling. - The label is attached, but its entire net — the local segment plus every other segment that resolves to the same name, on any sheet — reaches at most one symbol pin. A global label exists to connect its segment to somewhere else; if the whole net ends at the one pin it started from, the label is connecting nothing.
Two exemptions are built in: a segment that already joins two or more pins is never flagged (a label there is naming the net, not routing it), and a no-connect flag anywhere on the net suppresses the one-pin case.
In KiCad 10 the same situations report as label_dangling (unattached
anchor) and isolated_pin_label (net reaches only one pin) instead.
Common causes
1. The matching label at the other end is missing or spelled differently
A global label connects only to labels with the exact same resolved
text. VCC-PIC and VCC_PIC, nRST and NRST, or an invisible
trailing space all split what you meant as one net into two, and the
half with a single pin gets the warning. The other common variant:
the counterpart was renamed or deleted during an edit and this end
never was.
2. The label is intentional — a named spare pin or future connection
A spare connector pin labeled so the PCB net gets a readable name, a probe point, a signal reserved for the next revision. Electrically there is nothing wrong; ERC cannot tell a deliberate single label from a typo'd one.
3. The counterpart exists but its own segment connects to nothing
ERC counts pins, not labels. A matching label sitting on an empty stub of wire, or floating off-grid, contributes no pins to the net, so both ends keep warning — which reads as "one unused label when there are two."
How to fix it
Make the far-end label match exactly, or place the missing one
- Hover the flagged label and press the highlight-net key (backtick) to see how far the net actually extends.
- Search the label text with Edit → Find to list every occurrence, and compare spellings character by character — case, dash vs underscore, trailing whitespace.
- Rename until both ends are identical, or add the missing counterpart with Place → Global Label, and re-run ERC (Inspect → Electrical Rules Checker).
Use when: The label was supposed to connect to another part of the design. This is the common case, and a name mismatch is its usual form.
Delete the label if nothing should connect there
- Confirm with net highlighting that the label's net carries nothing you still need.
- Delete the label (and any stub of wire it rode on), then re-run ERC.
Use when: The label is a leftover — the circuit at the other end was deleted or reworked, and this end survived the edit.
When it’s safe to exclude
More defensible than for most checks. A deliberate single global label — a named spare connector pin, a probe net, a planned expansion — is a legitimate pattern, and right-clicking the marker → Exclude this violation records exactly that intent, one instance at a time.
Check the spelling of every same-named label first, because a typo'd net produces an identical warning, and a typo'd rail name is the kind of mistake that becomes a dead board. For the same reason, avoid downgrading the whole check in Schematic Setup → Electrical Rules → Violation Severity: the per-instance exclusion keeps the safety net while silencing the labels you meant.
Gotchas
- The check has a blind spot: a global label riding a segment that
already joins two pins never fires, even if the label appears exactly
once in the design. Your misspelled
VCC-PICbetween two chips sails through. Thesingle_global_labelcheck (added in 9.0, Ignore by default) counts occurrences instead — enable it in Violation Severity if typos worry you. - Read the marker's neighborhood. A lone
global_label_danglingwarning means a naming problem; the same warning arriving withpin_not_connectedandunconnected_wire_endpointfor company means the label's anchor missed the wire. - Buses are exempt from this check entirely; a single-instance bus label is deliberate policy, not an oversight.
Version notes
- KiCad 10.0: Check removed in this release.
Minimal reproduction
Wire a single symbol pin to a global label and connect nothing else to that net. In the schematic editor: place a resistor, wire one pin to a global label (Place → Global Label), leave the label's name unique, and run ERC (Inspect → Electrical Rules Checker). KiCad 9 reports:
[global_label_dangling]: Global label not connected anywhere else in the schematic
; warning
@(121.92 mm, 101.60 mm): Global Label 'SENSE'
The checked-in data/erc/samples/global_label_dangling.kicad_sch
reproduces this with one embedded one-pin symbol wired to a global
label. Because the file embeds its own symbol, ERC also emits one
lib_symbol_issues warning about the missing repro library; that is
an artifact of the self-contained repro, not part of this error. Adding
a second SENSE label wired to another pin drops the warning, which is
fix #1 in miniature. KiCad 10 does not report this code for the same
file; there the situation falls under isolated_pin_label.
Related errors
- Global label only appears once in the schematic (reference page coming soon)
- Label not connected
- Label connected to only one pin (reference page coming soon)
FAQ
ERC reports my global label as unused, but I placed it in two places — why?
The two labels are not resolving to the same net, or one of them adds nothing to it. Check for case differences, dash versus underscore, and trailing spaces — the match must be exact. And a counterpart on an empty piece of wire contributes no pins, so ERC still counts the net as ending at one pin. Highlight the net from each label and see where each one actually reaches.
Why didn't ERC warn about my misspelled global label?
In KiCad 9 this check skips any label whose wire segment already joins two or more pins, so a typo'd label between two components is invisible to it. Enable "Global label only appears once in the schematic" in Schematic Setup → Electrical Rules → Violation Severity; that check counts occurrences of each label name and catches the typo regardless of pin count.
Is it safe to ignore this warning on a spare connector pin I labeled on purpose?
Yes, once you have confirmed no other label was meant to match it. Right-click the marker and choose Exclude this violation so the exclusion is recorded per instance. Leave the check itself at Warning severity — it still catches misspelled net names elsewhere in the schematic.